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EZchip's Task Optimized Processing Core Technology

EZchip's innovative TOPcore® technology enables EZchip's network processors to deliver their exceptionally high performance. TOPcore technology integrates many high-speed processors; each optimized to perform a specific task. Four types of TOPs (Task Optimized Processors) are employed to perform the four main tasks of packet processing, i.e. parse, search, resolve and modify. A programmable TOP corresponds to each of these tasks, and performs its respective task exceptionally fast.

Each TOP processor type employs a unique architecture with a customized, function-specific data path and instruction set. This minimizes the number of clock cycles required for complex packet manipulation and provides exceptionally fast packet processing. TOP performance is boosted by a super-scalar architecture in which multiple instances of the TOPs are organized in a pipeline. TOPs - Task Optimized Processors

Four types of TOPs are featured, each tailored to perform its respective function:

Figure 1. TOPcore architecture employs an array of super-scalar processors.

TOPparse identifies and extracts various packet headers, tags, addresses, ports, protocols, fields, patterns and keywords throughout the frame. TOPparse can parse packets of any format, encapsulation method, proprietary tags, etc. TOPsearch uses the parsed fields as keys for performing lookups in the relevant routing, classification and policy tables. TOPresolve makes forwarding and QoS decisions, and updates tables and session state information. TOPmodify modifies packet contents, and performs overwrite, add or insert operations anywhere in the packet.

TOP processors are deployed in a super-scalar architecture featuring simultaneous parallel and pipeline processing. Multiple instances of each TOP type process frames at each pipeline stage, providing the power required for packet processing at wire-speed. Pipelining enables the passing of messages and pointers to packets from one processing stage to the next. Each TOP performs its particular task and passes its results (e.g. messages, keys, headers and pointers) to the next TOP stage for further processing.

Multiple TOPs at the same pipeline stage enable simultaneous processing of multiple packets. All TOPs of the same type execute the same code, however to maximize performance each TOP has its own program storage and operates independently of other TOPs.

TOP processors of each type are employed as shared resources without being tied to a physical port. An integrated hardware scheduler dynamically schedules the next available TOP to the next incoming packet. Ordering of packets is automatically maintained on a per-port basis.

When programming EZchip's network processors, the packet processing is reduced into four smaller independent tasks, i.e. four programs, one for each type of TOP (i.e. TOPparse, TOPsearch, TOPresolve, TOPmodify). Parallel processing at each pipeline stage is completely transparent to the programmer. Furthermore, allocation of TOPs to incoming frames (ingress or egress), passing results, messages, and frame pointers from one pipeline stage to the next, as well as maintaining ordering of frames is transparent to the programmer.

Memory Access

EZchip’s network processors feature embedded memory technology providing aggregate bandwidth of hundreds of Gigabits-per-second. Multiple embedded memory cores are used for packet buffering and for storing lookup tables. Additional memory is available through external DRAM. This provides the high memory bandwidth essential for packet processing and traffic management.

Arbitration of simultaneous accesses of TOPs to the various memory cores is controlled by an on-chip arbiter, and is completely transparent to the programmer.

Embedded Search Engines for Classification

EZchip network procesors integrate search/lookup engines that perform patented algorithms for efficient table lookups. Lookup tables are stored in embedded memory and low cost external DRAM chips. Since DRAM devices provide high bit density with low power dissipation and cost, they offer significant savings in the overall system design.

Use of DRAM for lookup tables has an added advantage of providing classification headroom for future growth. New applications that often require more and large lookup tables are supported through software updates only, without requiring additional hardware nor the redesign associated with it. This offers products based on EZchip’s network processors extended time in market.

Lookup Tables

Three types of data structures for lookup tables - direct access tables, hash tables and trees are supported. These data structures are used for implementing various forwarding, routing, classification, policy and state tables as required.

For each lookup table, the search key length and contents are programmable. The associated information stored with each table entry is also programmable providing the flexibility to support any type of classification and resulting actions. Tables can be of varying size and store millions of entries, and multiple tables/structures can be defined for storing routing entries, policy rules or other information.

Embedded Traffic Management

EZchip’s network processors also integrate traffic management with extensive capabilities. This enables provisioning of advanced SLA (Service Level Agreements) and bandwidth control for building networking equipment that delivers the application performance needed in carrier Ethernet networks.

After modification, packets are placed in queues that are managed and controlled by the embedded traffic managers and provide bandwidth and priority control on the ingress path, egress path or both. The traffic managers provide hierarchical per-flow and per aggregated flows, traffic metering, policing, Weighted Random Early Discard (WRED) congestion avoidance, priority-based and Weighted Fair Queuing (WFQ) scheduling and dual leaky bucket traffic shaping .

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